As the Internet and other communications networks continue to mature, high volume and high data bit-rate activities such as multimedia streaming and cloud computing are becoming more popular. To accommodate these wide data bandwidth applications, faster network services are required. To facilitate network services, network routers and servers typically include a serializer-deserializer system (SerDes). A SerDes includes a serial data link transceiver. A transceiver includes: (i) a receiver (RX), which receives high speed serial data and parallelizes the serial data into lower frequency, multi-bit data words and (ii) a transmitter (TX) which serializes multi-bit data words into high rate single-bit streams that can be sent over a serial communication channel.
FIG. 1 is a simplified block diagram of a conventional transmitter 100. The transmitter 100 is a serial data link, differential output transmitter. The transmitter 100 includes a serializer 101 and an output driver 102. The serializer 101 converts input parallel data into a serial data stream. The serial data is synchronized using the clock signal CLK. The output driver 102 may then send the serial data over a communication channel. The output serial data may be a differential signal with components TX_P and TX_M.
A conventional way to implement the serializer 101 is to use an N-bit shift register with parallel load. FIG. 2 shows an N-bit shift register 200 along with a corresponding timing diagram 250. The shift register 200 includes N two-input digital multiplexers (MUXs) 201 and N D-type flip-flops (DFFs) 202. N-bit parallel data is loaded into the DFFs when a LOAD signal is high. At every rising edge of the CLK signal, the data is shifted to the right, one bit at a time, generating the output serial data. The LOAD signal may be obtained by dividing the main CLK signal by N. However, the shift register 200 becomes impractical to use at higher data rates because of, among other things, the finite propagation delay of DFFs, finite hold and setup times of DFFs, and its large power consumption.
One way of handling higher data rates is to perform serialization of input parallel data in multiple steps. FIG. 3 shows a two-step data serialization system 300. The serialization system 300 may include shift registers 301, a serializer 302, and a line driver 303. An N-bit parallel bus is split into M smaller buses, each N/M-bit wide. M is selected to be a factor of N, such that N/M has an integer value. Each N/M-bit data bus is serialized by the shift registers 301 operating at a rate M times smaller than the rate of the system 300. The outputs of the M shift registers 301 are combined into an M-bit wide data bus, which is transformed into a one-bit stream by an M-bit serializer 302 before being applied to the input of a line driver 303. The line driver 303 may output the serial data in the form of a differential signal with components TX_P and TX_M.
The second stage serializer 302 may be implemented in a variety of ways using data multiplexers and latches. Sometimes the last step of the serialization operation is performed in the output line driver itself. However, since the output serial data needs to be synchronous, either a full rate clock, or a half rate clock with a duty cycle equal to 50% is used. When using a full rate clock, the serial data is synchronized with either edge of the full rate clock. When using a half rate clock with a 50% duty cycle, the data is synchronized alternately with the rising and falling edges of the clock. The generation and distribution of such high frequency clocks is difficult and consumes a large amount of power. Thus, there exists a need in the art to simplify clock generation and distribution circuitry and to reduce the power consumption of SerDes systems.